ESD – Understand and Test for Compliance (Part 1)

Electrostatic Discharge (ESD) . is a very common, yet often overlooked problem that can plague electronic equipments in a mysterious way. ESD is like an invisible, mischievous gremlin that come and go un-noticed, until the related failures or malfunctions become apparent. Yet, ESD by its elusive but superfast characteristics and very high frequency spectrum definitely belong to the EMI family. Once understood, the solutions to it are not very different than those for the more classical interference problems, bearing in mind that we will be dealing with a frequency domain up to the GHz, where some EMI solutions are simply not appropriate.

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1. The origins of the problem, a brief overview

Normally, for any material, conductive or not, the number of (-) charges (electrons) in each atom is exactly balanced by an equal number of (+) charges (protons), such as the net electrical charge seen from outside is null. If the material is an insulator, electrons do not move freely when subjected to an electric field, so if the materiel surface is being rubbed, or subject to sufficent friction with another material, with air or a non-conducting fluid, the peripheral orbits of the atoms will either loose, or capture some electrons. The result is a charge unbalance: the material may have lost a certain number of (-) charges, becoming positively charged, or acquired some extra electrons, becoming negatively charged.

 

The process by which components, tools, objects, people, vehicles, aircrafts, rockets, even clouds or water can become charged is extremely complex and multifacet. It would take at least an entire book for a decent coverage of the subject. Readers who are interested could consider some of the references given at the end. Following are some simple examples of E.S charging process: people shuffling their shoes on carpet or synthetic floor, clothes or underware rubbed against seats fabric, rapid flow of liquid, fuel, thin grains or even distilled water through isolated tubes, friction of rubber belts against ungrounded pulleys etc. Thousands of such episodes are causing ES charging that may end-up in more or less severe ESD events, if not dissipated properly.

 

An ESD happens when these static charges have built-up up to a point where the potential difference – say the excess of (+) charges, and / or the deficit of (-) charges ) is such as the insulation barrier – most often but not always air, is ruptured causing an abrupt recombination, usually with an arc.

 

Examples of Electrostatic charging scenarios: ESD is causing not only a discharge current, but also an intense electromagnetic fields over a broad frequency range, from (dc) to the low GHz, plus corona effects before and during a discharge. The ”culprit”, or intruder, is often a human, but it may be any object that is moved, such as a chair, an equipment cart, a vacuum cleaner. The victim is usually an electronic equipment or subassembly and is, although not always, at local static ground potential. It may occur that the equipment is ”victim of itself ”, whether or not it is in conductive contact with a human. Alternatively, a third party may be affected by the electromagnetic fields from a discharge between an intruder and a passive receptor such as metal chairs, carts, tables and file cabinets, as well as an other electronic equipment. Below are few typical systems where critical charge acquisition or release can take place:

  • Computers, office/business equipment, cash registers
  • Automatic selling and money telling machines,
  • Audio/video entertainment devices
  • Home appliances
  • Automobile dashboard displays / control
  • Industrial process controls
  • Hospital and medical care equipment

The Influencing Parameters

Several parameters are contributing to the E.S charging. The nature of the material(s) come first, with some dielectric, or merely insulating material being either on the Positive or Negative charging scale. Some notorious examples are Bakelite, acetate, Plexiglass or wool that rank very high on the (+) side of triboelectric series, while others like PVC, Teflon, Silicon are ranking way down in the (-) side. Next come the Relative Humidity (RH) and the temperature, given that the RH in turn is influenced by ambient temperature. From the above, it is easy to conclude that the worst conditions for E.S charging, hence for potential discharges (ESD) are a combination of:

  • Insulating materials on floor, furnitures, clothing etc …
  • Dry air, eventually with forced flow that tend to dry-up the moisture on surfaces
  • Low ambient temperature, because there is direct relationship between RH and To

A coarse criteria of the ability of materials to aquire, or bleed-off E.S charges can be based on their surface resistance:

  • RΩ/sq <106: border line of the conductors classification
  • RΩ/sq 106 -1010: AntiStatic, self-dissipative
  • RΩ/sq 1010 – 1011: AntiStatic, but not self-dissipative
  • RΩ/sq > 1012: Highly insulating, prone to E.S charging

Fig.1 shows examples of the ES voltages reached by people walking on different floor types, at different RH%. Fig.2 shows some typical situations of charge acquisition and discharge.

Fig.1. Electrostatic voltages reached by people walking on different floor types, at different RH%. The center column indicates the possible consequences on ordinary (non-hardened) equipment (source 3M).

Fig. 2. A few configurations of Personnel and Furniture Charge and discharges

Charasteristics of Discharge current for Human or Machine/Furniture ESD

Depending on the nature and size of the intruder/victim combination, culprit voltage and discharge current have different amplitudes and waveforms (Fig.3). Although ESD is referred to the charging voltage, the current is generally the most threatening parameter. Depending on the combination, we may have:

  • a human body whose finger (with or without a metal object) is touching the victim equipment (Human Body Model). The current is driven by the charging voltage and he body resistance.
  • a metallic, isolated machine touching an other passive device.Since the culprit has a low internal impedance, current can be high, limited only by the discharging loop impedance (MM, or Machine Model).
  • a discrete component (IC or encapsulated semi-conductor) touching a metallic part (CDM, for Charged device model). The current pulse will be extremely short, because of the limited culprit capacitance, but peak amplitude can reach several Amps.
Fig. 3. Waveforms and Frequ. spectrum comparison HBM, MM, CDM. Charged person/object discharging on a metal plate. Notice the 10MHz ringing wave of furniture discharge, due to its large capacitance and low internal resistance.

How serious is the ESD risk?

A crude, but interesting approach can be made by comparing the chance for an electronic equipment to be subjected to an ESD to that of an exposure to a lightning stroke. In Western Europe, the average number of lightning strokes is ≈ 3 per km2 / year, with a strong seasonal dependency and large statistical deviation around mean value. So, assuming an equiprobable distribution, the chances for a given location to have a lightning strike within a 100m radius is 0,1 /year. By contrast, in an office, a shop or a populated working area, the chances of a severe ESD to anything that people can touch are 1/day during cold / dry seasons, that is about 100 discharges / year. This means 1000 times greater risk of making ESD-induced errors than lightning-induced ones, if the victim equipment has not been properly hardened.

 

Between 1966-68, IBM researchers (Ref.1) recorded about 60.000 ESD events in selected areas choosen as typical of a reasonably high – yet very common – risk of static discharges by humans. The peak currents and RH were carefully logged and sorted by categories (Fig.4).

Fig. 4. Number of personnel ESD during worst case season in carpeted or vinyl-
floored areas (R.Simonic, Ref. 1).

2. Principal effects of an ESD

An ESD to an electronic device can result in different effects, depending on the way the discharge takes place, the undesired response (UR) of the electronic circuitry, and the criticality of this equipment operating mode. Two issues are considered regarding the ESD threat: solid damages to electronic components, especially ICs, and Errors/Malfunctions to an active equipment. We will look at the most common situations.

 

Direct Discharge to Microelectronic components (integrated or discrete)

Because of the minuscule size of their active devices, Integrated Circuits can be damaged by ESD, during their handling, packing/unpacking etc. (Fig.5). Given that the destruction threshold for μm size junctions is in the μJoule range, modern ICs, with thousands of devices per mm2, can be damaged by voltages glitches as low as 30 Volts on their I/O pins.

 

Fig. 5. ESD damages in microelectronics during handling

ESD failures occur by upsetting the breakdown voltage of the SiO2 isolation or overheating of the metallization. In MOS structures with oxyde thicknesses of 1000A.(10-7m), the rigidity of 5-7 MV/cm breaks if 50-70V are reached between two isolated channels. For a typical ESD duration, failure occurs by Joule effect whith junction or metallized trace melting like a fuse: when the current density exceeds 2kA/mm2, Aluminium particles migrate, reducing the available section in the conductor, which will blow-up above 30kA/mm2 or delaminate.

 

Plastic encased modules are more vulnerable because the field gradient creates arcing, or charge transfer from the case to the chip itself, that sinks to ground via the leads. Metal encapsulated modules have better chances to survive if the arc breaks over the can-to-benchtop air gap. But Fig 5(b) shows a reverse situation, often referred to as the ‘dead bug’: the metallic-canned module is standing leads-up an can be as badly damaged.  A variation of this is the ‘Charged Device Model’ (CDM). Since the through-resistance of the device and the discharge path can be very low, one can expect a significant peak current, on some pins, especially I/Os. Furthermore the package (leaded, unleaded, ball-grid, socketed or not etc …) also plays a significant role. An approximate corresponding, equivalent CDM circuit test set-up has been defined. Notice that, thanks to the low value of the devices self-capacitance (typically less than 20pF), the discharge pulse duration is only few nanoseconds.

 

A third possibility exist, similar to the furniture discharge when components or PCBs are manipulated by robots, automatic handlers etc. Here, the IC is handled by a massive equipment, some elements of which like rotating arms, jaws, conveyor belts, are poorly grounded or non metallic. This ESD threat for ICs, is known as the (charged) Machine Model, or MM (Ref. 2).

 

Antistatic Precautions in IC factories and Equipment Assembly lines

In all working spaces where ICs are manufactured or handled, the approach is simple, but rigorous: ” If we do not want ES Discharges, we must prevent the E.S charging of workers, tools, working surfaces, carts, packaging boxes etc”. This is achieved in practice by creating, and regularly controlling Static-Free work zones, with:

  • Static-free work areas and manufacturing hardware
  • Monitoring of % yields and chips infant mortality to detect ESD symptom
  • Antistatic precautions for PCBs handling in the field
  • Static awareness for employees
  • Ionizing blowers that inject constantly ions in the ambient air for compensating charges unbalance

Anti-static precautions should be applied all across the board (Ref.10). Nobody should handle modules without using a grounded wrist-strap or, at the very least, touching a grounded structure first; workbenches should be conductive, but ‘softly’ grounded via a few hundred kilohms resistor.

 

Direct Discharge to Electronic Equipment enclosure

The direct discharge is the most classical case, and the easiest to understand. A charged person or object (the ‘source’) touches a metal enclosure, the ‘load’. Most of the time (Fig. 6) the discharge occurs on a mechanical part which is touched intentionally (knob, key, switch, handle) or fortuitously (frame, covers, connector shell etc…), but there some more severe occurrences may happen:

– Finger approaching an unprotected I/O connector

– Finger arcing through, or arc creeping around, a LED or Indicator display

– Discharge on a PCB mounted switch, in which case a subsequent arc occurs internally between the toggle and the active contacts of the switch)

 

In these cases, the ESD current could reach directly the electronic components by a conducted path. Except for some damping caused by the wire or trace length, the situation is almost as severe as the direct discharge to a module pin, as explained above.

Fig.6. Examples of severe ESD with direct contact.

Whatever the scenario, the current returns to ground by all possible routes, with amplitudes pro-rated to the impedances of these respective paths. This means that the bulk of the current will flow by the lowest impedance path, the remainder flowing through all other possible routes. Fig.7 illustrate some of these routes for a single stand-alone machine.

 

If we go back to the actual waveform of a hand/metal (the most severe) type of personnel ESD, seen in Fig.6, the sharp peak of initial current caused by the local discharge of the forearm-to-target capacitance does not return by the machine-to-ground path. Instead, it remains confined into the loop formed by the hand and the machine cover. Only the main part of the current pulse, with rise time of 5-10 ns is reclosing by the machine-to-ground impedance. So, it seems that the discharge current should sink via the machine safety-ground wire (Fig.7, left) and/or its neutral wire (grounded at facility level). But the self-inductance of a 2m a wire is 3μH. For a 5 ns current rise, the dynamic impedance will be:

notwithstanding the additional length of building earth wire. The entire ESD current will not choose a 600 ohms path while another, lower impedance one exist in parallel. Any machine has a stray capacitance to ground. With a metallic casing, this capacitance can reach 100 or even 1000 pF. A cabinet with a bottom area of 1m2, located 8-10 cm above ground has a parasitic capacitance of 100 pF. For a rise time of 5 ns, this is a dynamic impedance of about 50 ohms. Therefore a large proportion of the ESD current (specially during its rise, the most threatening one) will sink via the chassis-to-ground stray capacitance.

Fig. 7. Personnel ESD coupling routes, showing return current paths.

 

Fig.7, right, shows a third possibility – the reverse discharge. In this case a machine has been charged by:

  • successive previous discharges from people and objects
  • internal static generations
  • laminar flow of air, specially dry or cold, or rubbing against a dry, isolated material.

 

If the machine is floating vs ground (table top equipment with power cord not connected, battery powered device etc..) the recombination of charges is not occurring, or very slowly. When somebody approaches the machine, or take the power cord to plug it, a discharge will occur. The resulting surge creates locally a power line transient which may affect other machines nearby.

Indirect discharges

With an indirect discharge, the person does not (or cannot) discharge directly on the equipment. For instance, a machine entirely housed in plastic with no or few accessible metal parts, cannot be discharged on. With the massive arrival of plastic housings for electronic office products and data terminals, it was first expected that they would mark the end of the ESD nightmare. It was quickly found that these products were having even more ESD crashes than those with metal casing! Fig.8 shows what happens: a person discharges on any nearby metallic part: a door frame, a water pipe, a furniture, maybe the very desk on which the machine is standing. Then, the ESD pulse radiates a strong local electro-magnetic field, which couples into the nearby electronics since a plastic enclosure offers no shielding. With a desktop machine, for instance, if the mother board lies flat on the bottom of the unit, the PCB is within 2 or 3 cm of the ESD current path, with the signal traces acting as receiving antennas.

Fig. 8. Two Scenarios with Indirect ESD coupling

Induced Errors / Malfunctions

Putting aside the damages caused by Direct Contact to an accessible, active circuitry, the main concerns are the induced effects caused by a fast-changing ElectroMagnetic field close to the discharge path. At the very instant of the discharge, a strong local field excitation takes place:

  • The electric (E) field, that established at a high value by the chargedbody, is collapsing abruptly
  • A magnetic (H) field caused by the discharge current suddenly raises to a large value

Both dE/dt and dH/dt field derivatives are playing a role, but experience have confirmed that the most severe threat is related to the magnitude of the current, hence the H field. Tests have shown that a machine standing 10kV ESD with a generator having 2kΩ of internal resistance will fail at a lower level with a tester having only 150 or 300 Ω of internal resistance. In most cases the victim electronic circuits are not in the path of the ESD current, which flows usually on housings and metallic structures. It is the near field coupling by which the field created by the discharge induces a voltage spike into the exposed circuit.

Fig. 9. Simple model for radiation coupling from the ESD current

Fig. 9 shows a simplified model of this phenomena, based on the discharge current only. The size of the ESD generating circuit being large compared to its distance to the receiving circuit, simple solutions of Maxwell’s equations for small E,H doublets cannot be straightly applied. A rigourous approach would use the method of moments, breaking down the current path in small segments. The simpler model shown assimilates the current path to a long radiating wire, for which the resulting magnetic field is easy calculated. The ESD drain path being long versus the observation distance, the magnetic field is given by:

If the area of the circuit illuminated by the ESD field is known, a derivation of the field over the rise time gives an approximation of the open loop voltage induced, sufficient for a quick prediction:

Re-arranging Eq. (1) and (2) and and using more convenient units results in:

Example: For a 4kV-15A ESD with tr = 1ns, two printed traces one cm apart, with a 5cm parallel run, located at 10 cm from the ESD flow will see a peak transient of 2x15x 5 cm2 / (1 x 10) = 15 volts. This is enough to create an erroneous bit in most logic technologies.

 

Although very basic, this prediction of the induced parasitic voltage gives adequate approximation, when compared to actual measurements. Eventhough the current flows more as a spread stream than like in a thin wire, the H field around its path can still be found by equ.(3). This field from the ESD pulse has two effects:

 

– it couples to the inner circuits of the machine: circuit boards, flat cables, discrete wiring,

– it illuminates also the outside, all around the ESD source and discharge path where external signal and power cables behave as receiving antennas as well.

 

Another critic could be raised: the discharge current flow is supposed to stay confined on the outer face of the metallic cabinet because of the skin effect and, according to shielding theory no current should be found on the inner side. This would be true if the whole housing was an homogeneous shield, which is not the case: slots, joints, vents, displays, cable entries create leakages especially at these high frequencies. As a result, the ESD current excites the slot antennas formed by the box discontinuities. For the high part of the ESD spectrum that approaches or exceed their λ/2 resonance, they shine inside with practically no attenuation. With a product not especially EMI shielded up to 1GHz, the ESD current will flow on the inside of the cabinet as well as outside. And itis the high frequency contents of the ESD radiated field that induces the largest voltages in the exposed PCB traces and in the cables.

 

Notice that since most ESD-induced malfunctions are related to the current (or field) derivative, a 1kV hand/metal ESD with 0.3 nsec. Rise time can be as much threatening as 4kV with 1.2 nsec rise time. The two induced disturbances have the same amplitude, the difference being in their duration. Considering that in a given environment there are statistically much more 1kV discharges than 4kV ones, this would lead to an ESD test plan imposing more error-free discharges at lower levels (see further “Error per pulse criteria”). Yet, knowing just the magnetic field may not be sufficient. In certain cases, a deeper knowledge of the nature of the electromagnetic field near the ESD path may be needed (Ref 2,4) .

3. Testing can guarantee a reasonable ESD immunity

Until the early 1980’s, EMC and ESD seemed to be two different worlds. In many companies, the same people were wearing the two hats …. but these were still two hats. EMI susceptibility studies were checking the behavior of equipment exposed to steady electromagnetic ambient fields and power line disturbances, while ESD tests attempted to reproduce human or furniture discharges and their effect on fragile circuits. Yet, testing for ESD vulnerability is one of the most important, versatile and relatively easy to perform of all the EMC tests. Thanks to its huge bandwidth, greater than 300 MHz, and to the strong field created locally, the test can reveal all at once many weak spots of a design (PCB, wiring, box shielding, I/O ports filtering), that could have taken a much longer time to detect by classical methods, such as radiated susceptibility that requires a shielded/ anechoic room, large antennas and powerful amplifier.

 

However, as simple as it may look, a sound ESD testing requires an accurate, reproductible test set-up. Early tests of the 1970’s were often a ’hit or miss’ game. Product designers had to content themselves with foggy reports like: ”the equipment stands 2kV but fails at 6-8kV”, with results depending on where, when or by who the test was done, the test arrangement bringing also some discrepancies. Those days are gone, but an ESD test giving dependable results requires a careful test plan, the core of the test set being the generator.

Personnel ESD test and simulators

Human Body ESD is the most commonly practiced test, but it is presomptuous to assume that an assembly of discrete capacitors, resistors and wires will act in the same manner as the capacitance of a human body, that is distributed over a wide surface. No actual ES Discharge is really alike from one event to another. So, an ESD simulator and its set-up has only a vague resemblance with the circuit of an actual discharge, but it is agreed that this artificially-created ESD is an acceptable ”like-if”. A sound personnel ESD test should be able to simulate air as well as contact discharge, and Direct / Indirect ESD.

 

The earliest ESD generators were quite rough, even sometimes home- made devices. Since 1970, many ESD simulators – quickly nicknamed ”guns” or ”zappers” by the EMC community, have been marketed, the most recent ones being thoroughly designed, with better reproducibility of the rise time, accuracy of H.V. setting etc. These simulators are based on the simplified model of human body with the R,C network packaged in a compact, generally hand-held, unit. A capacitor is charged by a high voltage DC supply, then discharged on the equipment under test (EUT) through a determined resistance. One armature of the HV capacitor is connected to the injection probe, generally shaped like a finger. The other armature is connected to the reference ground or any desired return path. To perform ideally, the simulator should have preferrably the following features:

  • variable ESD voltage, easy to set with an accurate read-out, selectable positive or negative discharge
  • the ability to deliver up to 3.7 Amp/kV in shorted output mode, with 0.5 to 1ns risetimes
  • several (at least two) interchangeables discharging resistors, for inst. 330 to 2000Ω for personnel and 10 -50 ohms for furniture, along with several capacitor options.
  • the ability to generate a discharge with, or without an arc
  • shot counter, for a known number of discharges on each point
  • a time-out device disabling the HV probe when a preselected number of shots isreached.
  • an option of choosing single shot or a repetitive mode, for inst. slow rate (0.5 to 5 pulses /sec) for formal testing and accelerated rate (50 pulses/sec) for investigations.
  • an alarm (audible or visible) in case of aborted, or sputtering discharge (restrikes).
  • a way to bleed-off the charge from the tip in case of discharge to floating parts
  • a ground return connection hardware which is safe, convenient and idiot-proof
  • an automatic safety latch that removes the HV from the tip when the gun is at rest.
  • high quality components in the high-voltage section, for a long life expectancy, since an EMC lab performing routinely ESD testing can make 50.000 to 100.000 discharges /year .

Arc or Direct Contact?

One testing dilemma is the following: should the simulator replicate by all means the conditions of an actual discharge, by arcing, eventually to the expense of losing some reproducibility? Or, should we sacrifice the arc conditions and inject without an air gap a calibrated pulse waveform, that will stress the EUT ”as if” it were the actual event, eventhough the electrical mechanisms are not all there? Both approaches have their pros and cons. However given some constraints implied by the physics of high-voltage switching, the following trade-off was adopted by most ESD standards:

 

a) Contact discharge is preferred up to 8kV, because it avoids the randomness of a self-triggered arc. Instead of an airgap discharge, the HV is applied to the tip by a fast, bounceless relay, contacts being in a sealed bulb with vacuum or high-pressurized gas. This guarantees a clean, ”sanitized” waveform.

 

b) Air discharge is used in the following cases:

  • for testing above 8kV up to 15kV, or more for some standards
  • for testing at any voltage where a direct contact by the pointed tip is not physically possible.

In both cases, the pointed tip is replaced by a spherical, 8mm diam. finger-like tip.

Simulators for equipment test, based on IEC 61000-4-2 Standard

Since this standard is enjoying international acceptance, as a baseline for assessing ESD immunity of many products, the corresponding simulator will be briefly described. It is based on the simplified equivalent circuit of human body ESD, but with a discharge resistor of 330Ω, instead of the 1 – 2 kΩ, more typical of human models (Fig.10). The 150pF storage capacitor is charged through a10 to100MΩ limiting resistor, providing a maximum charging time constant RC of 15 msec, such that after ≈ 0.075 sec (5 x RC) the capacitor is fully charged. The 330Ω value for the discharge resistor, replacing the early 150Ω versions, has several advantages

 

a) for a given inductance L of the complete discharge loop, it forces a smaller L/R time constant, hence a faster rise for the main discharge current.

b) it is close to the statistical low value for human body resistance in the kV/nsec region. However it makes the waveform departing even farther from a furniture high current ringing pulse.

c) tighter tolerances for the current and rise time, contrasting with earlier simulators that indulged too much on unacurracy.

d) The sharp precursor effect of dry air hand-metal discharge is controlled, instead of being left to chance.

e) The current calibration with a zero-inductance coaxial target eliminates the influence of the ground return strap on the rise time of the first peak. The pre-discharge being generated at the probe itself, and with a higher value of the discharge resistance, the ground strap has less critical effect, the main current hump being somewhere between 10 to 30ns after the initial peak.

Fig. 10. IEC 61000-4-2 simulator characteristics. Current waveform is measured via a 2 Ω coaxial target, in a shielded enclosure. No tolerances given for the air discharge, assumption being that a generator capable of meeting the current template will deliver a correct air discharge waveform.

Several manufacturers worldwide are offering ESD generators conform to IEC standard, with various hardware options. One of them, the Keytek MiniZap has been the workhorse of many test labs for more than ten years and constantly improved.

 

A certain number of applications like automobile electronics, aircraft and aerospace equipment, electro-explosive devices etc… require different RC networks. Most modern IEC-type simulators have such options, offered as user-replaceable modules (Fig. 11). In this case the current and waveforms can differ from the original IEC definition. Ultra-high voltage ESD generators are required for automobile and airborne equipment tests. Because the physical nature of their environment: high static buildup in a confined space, isolated from ground), and the life-threatening consequences of some ESD-induced failures, like airbags, braking/ABS, door-locks etc… test voltages higher than the maximum severity of the IEC or ANSI standards are required.

Fig. 11. Example simulator with easily interchangeable discharge modules (Courtesy of EMC Partner)

Furniture vs Personnel ESD simulation

Furniture or large objects discharges create waveforms, hence frequency spectra and induced effects, that differ from personnel ESD. While in near field region the higher voltages of personnel ESD creates a strong E-field transient but low H field, furniture ESD by its low source resistance creates stronger H-field. Because of the longer duration of the ringing wave, the induced voltage in exposed electronics can be more disturbing, especially with medium speed circuits.

 

This is not saying that a product passing a furniture-type ESD test would be implicitly immune to personnel ESD, rendering this latter test needless: furniture discharge is not likely to take place on all areas of the EUT, and its lower voltages (always below 5kV) do not permit arcing on many hidden or recessed areas. In addition, the super fast rise time of hand/metal personnel ESD creates intense E-field transients not present in furniture discharge. Given 3 discharges with ≈ similar probability of occurence, the respective frequency spectra of personnel (direct hand/metal and air discharge) and furniture ESD, show that furniture spectrum overrides the others in the 10-30 MHz range. We remark that:

  • A single test based on personnel ESD alone ( Rd > few hundred ohms) may overestimate the equipment immunity to furniture ESD.
  • A single test based on furniture ESD alone (Rd < 50 ohms) may overestimate the equipment immunity to personnel ESD.
  • Although it simplifies testing, a trade-off discharge network with 330Ω resistance and approximately 2μH of loop inductance does not replicate adequately the large oscillatory current of furniture ESD.

Thus, strictly speaking, a fully representative test program should include both personnel and furniture ESD (Ref.2, 5). If the manufacturer’s objective is merely to design a product that passes the tests and comply with the requirements for a CE mark or other approval, the personnel ESD test is a decent shelter, but it carry the risk of a compliant product that will sometimes fail in the field. Testers capable of reproducing both furniture & personnel ESD have been commercially available. IBM Kingston EMC engineers had developed for their own use an ESD tool (also made by Handy Hish Co) that performed efficient and repeatable tests, thanks to a crossed-vanes structure, replicating the distributed capacitance of a human body, or metal cart, standing close to the EUT (Ref. 10). Commercial versions were marketed after 1990 by ElectroMetrics and Keytek, but not widely used.

4.3 ESD simulators for component testing (survival testing)

A special category of ESD testers exist for component vulnerability per Mil Std-883 or JEDEC /ESDA for instance, that inflict a given ESD level to every possible pin combination of an integrated circuit (or any ESD-sensitive component). These tools no longer look like a hand-held gun but rather as a work-station with a programmable module socket. The selected IC pin(s) and the test can be automated with complex test sequences that the user can program. Discharges can be configured for HBM, and Machine or Charged Device models. The test results are visualized on a curve-tracer or screen, displaying the I,V curves of the stressed device, printing an overall test report etc…

 

All these features are no luxury: assume, for instance, a manufacturer who has to monitor regularly the ESD sensitivity of a 56 pins IC. That makes 56 tests, times two polarities, and a statistical distribution of the failure levels is necessary. Therefore, the voltage will be gradually increased from 500 V to 4000V, by 250V steps, with each pulse repeated 5 times. For the sole HBM, the total number of measurements to take, depending on the spread of the devices characteristics, will vary between:

 

56 x 2 x 5 = 560 for those devices failing after the first voltage step, and, 

56 x 2 x 5 x (4000 – 500)/ 250 = 7840 for those devices who resist up to 4000V

 

It is of course out of question to have these tests done manually.

 

Fig.12. Basic set-up of an ESD Test and HCP / VCP arrangement for Indirect ESD.

4. ESD test set-up, direct & indirect ESD

The basic set-up for ESD testing is shown on Fig.12. The EUT is normally installed above a ground reference plane (GRP), at a height dictated by its wheels, feet, casters etc. By default, 5 to 10cm insulated spacers can be used. The GRP is the common reference for all the elements of the test: the generator return wire, the EUT and the various accessories. Several variations of this basic installation will be described, especially when the EUT housing is not entirely metallic. The metallic, copper or aluminium GRP must be present every time to stabilize the EUT-to-ground capacitance, thereby allowing repeatable testing. Without it, the return path of the discharges would be uncontrolled, shared between some undefined earth plane and the room/ building earthing wires. Thus the rise time and the spread of the return currents would differ, making the test not reproducible from one set-up to another. For preventing the GRP from rising to an undefined potential after repeated discharges, creating test unacurracy or shock hazard, the plane is connected to the local earth terminal. This safety earth connection has no importance for the high frequency response of the test.

Direct vs Indirect ESD Test

The EUT-to-ground configuration can be more complex than the simple sketch of Fig.12. The EUT can be an upright, floor-standing machine, a table top equipment or eventually a wall-mounted device. It may have a metallic housing or a non-conductive one.

 

Roles of the HCP and VCP: with IESD that aim at reproducing the scenario of a charged person touching a metallic structure close to a non-metallic product (“Indirect ESD”), HCP and/or VCP are specified (Fig.13). The HCP simulates the case where the EUT is resting on a metallic desktop, the gun being discharged on the edge of this metal plate. All the same, to simulate the case of an EUT close to a large vertical object, the gun is discharged on the edge of a 0.50 X 0.50m vertical coupling plate (VCP). The following recommendations are addressing these different options.

 

A) For equipment with metallic housing ( Direct ESD)

A.1 If the EUT is floor standing, it should stand over the GRP, as shown in the basic configuration of Fig. 4.17. As default value a 10cm height above ground is generally adopted, except when an other height above a conductive floor is defined by application constraints.

 

A.2. If the EUT is a table-top equipment, most standards ask that it should rest on a non-conductive table, an HCP being added to simulate the coupling with a metallic table. A legitimate question arise: why select a wooden table, then simulate a metallic desk by adding a sheet of metal, instead of using always a metallic table ? The coupling of the EUT to the floor-level reference will be different wether it is resting on a metallic top, or not. Deciding which one is the ESD worst case is very speculative, as it depends on the internal design of each EUT and its I/O cables arrangement. So the standard set-up of IEC is a fair trade-off, since it is easier to turn a wooden table into a metallic desk-top than doing the reverse.

 

B) For equipment with plastic housing ( Indirect ESD)

B.1. If floor standing, the EUT is installed on a GRP, as for case A.1.However, since there are no or very few accessible metal parts for direct discharge, the test procedure will apply:

  • Direct ESD on all eventually accessible metal parts
  • Indirect ESD by discharging the probe on the VCP, grounded via high value resistances to the GRP. Discharges will be made at 10 cm from each side of the EUT (10 cm is deemed to represent a reasonable worst case where people will actually discharge on nearby metallic objects). Yet, for some specific products, other distances can be selected.

B.2. For table top equipment, the EUT is installed on a non-conductive table, covered with the HCP as in A.2. The height of the EUT above this plane is simply dictated by its feet or stand-offs. No incidental contact to the HCP should occur by protruding metallic parts on the bottom of the EUT. This is usually achieved by putting an insulating foil on top of the HCP. A VCP will be installed on the HCP, via an insulating stand. The test procedure will apply:

  • Direct ESD on any accessible metal part (switches, keys, screws, conductive elements of an otherwise plastic cover, etc…). This imply contact or arc, whichever comes first.
  • Indirect ESD by discharging the probe on a VCP (like with B.1), and on the table top HCP, following a perimeter about 10 cm from the EUT sides.

Much discussion and controversy exist about some test variances, which are not fully resolved in the IEC and major testing standards:

  • The connection of the HCP (or VCP) to the ground reference plane (GRP)
  • How should the VCP be located with respect to the actual EUT target zone?
  • Are the VCP and HCP required regardless of non-metallic or metallic type of EUT.
  • Rationale for using a VCP for EUTs with a very low height-to-perimeter form factor,
  • Variation of the E and H fields generated by the gun’s head with its tilt angle on the HCP/VCP.

Grounding of the simulator and of the EUT

The EUT is grounded normally to the safety earth terminal of the power outlet. For EUT with no earth conductor (class II equipment) or battery operated, it will then be un-earthed. In no circumstances should the EUT be directly grounded to the GRP, unless this is the way it would be normally installed, as for instance airborne or automobile equipment. The return path for ESD pulse to the generator must be a 2m strap, screwed or bonded to the GRP via a clamp. The simulator should not be grounded to the EUT frame or the table-top HCP, except for some exploratory diagnostics. When the EUT is not grounded, its floating metal parts must be discharged after each ESD by touching them with a grounded wire through a few 100kΩ resistor or some bleeder network.

External cables and Influence of System configuration

Quite often, the test has to replicate the actual conditions of a system. For instance, the EUT may be one unit of a multiboxes set, where the vulnerability must be evaluated by testing one box after the other. Alternatively, the EUT may be designed as stand-alone, ”attachable” to several types of peripherals or ancillary products which must be connected to the EUT, even if they are not themselves being tested. The non-tested units must have an immunity level consistent with the ESD test objective. The whole system being installed over a GRP, all the external cables which are connectable to the EUT should be in place as in a typical installation. To avoid too much variance in results, they should be laid at a constant, repeatable height above the ground plane, like 10cm.

 

Propagation of ESD impulse currents in a multiple-units system is dictated by the Common-Mode (CM) impedances of the system cabinets and cables with respect to local ground planes (i.e. floor, but also walls, ceilling, concrete rebars etc…). Depending on the actual configuration: number of extensions connected, I/O ports used etc… and on the installation variations: non-conductive or metal desk, non-conductive floor, raised metal floor etc…. an infinite number of CM impedance combinations exist for the ESD current to spread from the victim unit to the companion units.

 

As a result, the whole system ESD susceptibility can deviate significantly from that of its individual units. Eventhough it is recommended that each one be tested with its I/O cables installed and terminated “in a representative manner”, one can predict that its behavior will be different in a complex network (Ref.2, 8). If the unit is tested with all cables laying 10 cm over a metal plane, this is regarded as a worst case since the low CM impedance of the cables will invite a larger share of the current to flow, for a same ESD initial voltage (remember: ESD, especially the personnel type, is a current source). The share of the total ESD current will be greater for the cables. If this same unit is used in a small system configuration (i.e. not all I/O cables are present) and the cables are mounted high above ground, the box will take a bigger share of the ESD current and some failures related to apertures leakage and coupling to PCB may become predominant.

 

All these aspects result in frustrations observed in the system ESD performance, compared to its units individual performances. Futhermore, higher ESD amplitudes do not necessarily mean the worst threat for unit / system performance since current waveforms neither exhibit a constant rise time (hence, bandwidth) or a constant Amp/ns slope that would result in a constant Amp/MHz spectral density in the high frequency portion. Thus, when a unit is designed (or hardened) for a given ESD severity criteria, it must be checked, during design and test that:

  • The level which has been achieved fo the maximum system configuration (all possible cables, features and peripherals installed) is still met for the minimum size, or eventually a stand-alone configuration.
  • This immunity does not rely exclusively on a drastic treatment of the I/O cables and interfaces. A good ESD performance built upon an intensive use of well-shielded cables and capacitive decoupling of I/O ports may deteriorate when the unit is not equipped with all these cables.

With complex systems, it is sound to develop for all the transient immunity tests – not just ESD- a software which exercises every special purpose routine that operate specific hardware areas. This will give a better efficiency for approaching a 100% probability of shooting in the worst sensitivity window, without running an excessively long test.

5. ESD test routine and discharge procedures

1) Preparation:

Determine a clear, indisputable malfunction status such as hard-error, wrong read-out, inadvertent reset, alarm, power-down etc …that can be detected without the need of an external oscilloscope or data-logger. This point is important: No external ancillary equipment should be used to diagnose a fault condition, because the very presence of additional cables, or the monitoring device itself, can cause the EUT to fail at lower levels, hence wrong test results. The only exception would be a fiber optic link to dectect a change-of-state of some signals.

 

If the EUT is a programmable device, it may be useful to develop a test routine which:

– exercises continuously all EUT operations, in closed-loops without requiring an operator

– indicates clearly by a print-out, visual message, alarm, buzzer, dead display, locked keyboard etc…, that a fault has occured.

 

Make a zoning by dividing each side of the equipment into approximately 0.1m2 (30 cm x 30 cm) areas. Mark/Code each ESD target area. Include signal cables and power cord entry areas. Determine if the discharges will be entirely direct (D.ESD), indirect (I.ESD) or hybrid (Fig.13).

Fig. 13. Decision chart for discharges mode. Notice that a D-ESD is practically always to be attempted on plastic coverd products, because of the possibility of few metallic targets.

 

2) Application of the discharges

Set the ESD level at about 3kV (for a personnel discharge) or other determined value, depending on wether it is an investigation or a QC test, and discharge on each coded area. If this area includes switches, keys, indicators, connectors, screws, rivets, etc., apply the discharge on them. Apply also the discharge on the seams, slots, display edges and any protruding shape or surface discontinuity. Otherwise, simply apply the discharge in the middle of the coded zone.

 

If the EUT housing is plastic, perform indirect ESD on the HCP and VCP, at 10cm from the target face. A direct discharge should still be tried on screws, rivets, decorative trims, etc. Do not forget EUT areas which are accessible only under specific circumstances, like:

– parts touched by end-user during service (batteries, cassettes, ink cartridges.. etc).

– I/O connectors not equipped with their cables

 

Such zones should be tested with a minimum requirement of No Damage or No Permanent Change of Conditions (loss of data, alarm… etc). Apply air discharge (spherical probe tip) on those targets which cannot be touched by direct contact

 

3) Repeat the discharges, until the prescribed number have been applied without unacceptable EUT response. If no minimum number of pulses is prescribed, use 50 as a default, in each polarity, but the minimum number of pulses to guarantee the test depends on the complexity of the EUT operations. Repeat step 3) for all coded areas and record which ones failed. If none failed, increase the level by 1kV and re-run the test. Above 8kV, most specs recommend changing from contact discharge (pointed tip) to air discharge (ball tip).

 

4) For each failed area, decrease the ESD level to find the Go/No-Go threshold, and record it.

 

5) Starting with weakest spot, apply EMI hardening methods, until meeting the test objective.

 

Determine a ”sure-to-fail” ESD voltage: many simulators have a selectable repetition rate, since manually applying 50 discharges times ”n” points in a single-shot mode would be tedious. Also, for a first look-out at a low ESD voltage, a quick sweep of all the target zones with accelerated pulse rate like 20-50 pulses/sec can give a coarse estimate of the immunity, saving a lot of time. This first scan, intuitively thought as way to detect the weak spots, is in fact a way to eliminate the non-weak spots, thanks to an accelerated pulse rate. Within 1 minute at 50 pulses/sec, 3000 discharges are been injected, giving a confidence that the selected area is fairly immune. Then, and only then, the areas which did not pass this first exam. are candidates for a deeper search. These we will re-test to the number of specified discharges, but with a slower repetition rate, allowing EUT self-recoveries (if any such feature); Otherwise, it could lock-up in a repetitive error mode, misrepresentative of real ESD situations (there are never several ESD events per second).

 

Another phenomenon may occur if a too fast discharge rate is used. After many repetitive pulses, circuits with high input resistance, or their 0-Volt reference floating, will accumulate charges because of their large RC time constant reaching tens of millisec. The ”stacked” voltages may accumulate, causing an upset that did not manifest at the first discharge Therefore, because of these possible EUT responses mentioned above, it is safer to slow down the pulse rate, checking wether the “fail” level is correlated with the pulse rate. What matters is the minimum number of pulses to apply, not their repetition rate. Test results must be arranged in an orderly manner, allowing one to keep an accurate track of the failing zones, record the fixes that worked and those that did not; Too often, this is neglected and people have to ”re-invent the wheel” at every test. A dual indication ”Run/Fail” is also recommended.

6. No error / No damage concept: The several layers of severity

A hierarchy must be decided regarding the pass/fail criteria: Fugitive, self-restoring errors, Non-recoverable hang-up, or unexpected upset ? Hard failure ? Like any surge-type test, testing for ESD involves threshold criteria. Before testing, the designers of the EUT as well as the test people must clearly define what is to be considered a failure. Some refinements can be introduced, like:

 

a) malfunctions were only soft, self-recovered errors ?

b) malfunctions were hard errors, requiring user’s intervention (reset, repower)

c) malfunctions were hard errors plus loss of data requiring user’s intervention

c) there was solid damage, requiring repairs.

 

The ”Fail” criteria may also depend on the type of product and the type of market. For instance, in selecting the actual ESD test voltages one should consider:

  • Likelyhood of high human activity around this product
  • Type of environment (controlled or uncontrolled R.H., anti-static floor carpeting etc…)
  • Sensitivity of the user to a temporary malfunction or error, i.e. how often a week or a month can a malfunction occur is considered ”tolerable” by the user ?

The following stepped scale is a frequently used Pass/ Fail ESD criteria:

 

Up to V1, the lower level, no malfunction at all (recoverable or not) is tolerated. Consider for instance an airline reservation terminal which exhibits recoverable errors for 3kV personal ESD. The number of ESD events > 3kV in a counter type of environment is very high. Even if errors are automatically detected and the transaction is cancelled, then retried, this terminal will spend too large a percentage of time recovering from errors, especially during the winter/spring season.

 

From V1 to V2, errors are permitted if ”transparent” to the user, i.e. they are self-corrected, not requiring a user intervention to restore normal operation.

 

Above V2 and up to V3, ”hard” errors are permitted, such high level having a low probability of occurence, not upsetting the user if an operator intervention can resume normal. It may be required that the error be visible to the user, since it is not automatically corrected. No damage is accepted, or unsafe condition leading to safety hazard, or high financial prejudice.

 

The ESD test levels per IEC 61.000-4-2 are only indicative: each industry or government agency decides the ESD immunity level for their respective products and applications. Examples of such categories are:

 

Household Appliances & Entertaiment Devices: High human activity, uncontrolled environment with aggravating factors but useage is rather fault-tolerant as long as there is no solid damage.

 

Office Products, Small Business and Point-of-Sales Equipment: High human activity, uncontrolled RH (can be as low as 15%), with any type of floor/carpet . Irritability factor quite high, partial alteration of data not catastrophic because generally detectable by operator/user.

 

Large Business Computers, Scientific or Medical Facilities, Systems handling Critical data (Banks, Government etc.): Require a high reliability, hence a low Error Rate (ER), but RH, floor treatment and general environmental factors are well controlled.

 

Coherent ESD test criteria, adapted from ANSI.C63-16 are given in Table 1 They correspond to discharges applied with a 330Ω/150pF IEC or similar ESD simulator. Test levels are for data processing equipment (officially designated ‘Information Technology Equipment’ or ITE). Two environment classes are considered:

  • Controlled environnement: RH always > 20% and anti-static floor material
  • Standard ( yet severe) environment: RH as low as 10% for some periods, and synthetic carpet

No test levels are indicated for furniture discharge, since this test is not widely practiced.

Table 1. Suggested personnel ESD Test values for Data Processing Equipment

7. The error per discharge concept, or multiple trials approach

Not exclusive of, but rather complementary to the severity layers, another concept, the error-per-discharge probability has been recommended, although not widely used. Rationale for this is explained in Ref.2,6,7. The basis is that the Unwanted Response (UR) of a machine is a probabilistic encounter between a randomly occuring event (the discharge), and the “window” of the most vulnerable configurations of certain critical logic inputs (Fig.14). The collision of these two random events cannot be predicted by a deterministic approach, therefore any ESD standard, requiring simply a minimum of 10 discharges without errors is ill-feated.

 

The unwritten, implicit statement that “if the EUT did not fail in 10 discharges, it will never fail” is as stupid as throwing a pair of dices 10 times and deciding that if you do not get 2 aces, you will never get 2 aces. Instead, the fail/ no-fail decision must be based on a large number of independent trials, that the theory of probabilities help us to define. The rationale is that the error sensitivity of a machine to ESD is never a step function. An ideal behavior (Fig.14, curve A), is a machine showing no error at all (regardless of how many pulses) below a given ESD level, then making one error /pulse, that is P(error/discharge) = 100%, above that level. By comparison, the behavior of an actual machine (curve B) is plotted as the number of errors per ESD event, which is less than, or equal to unity. Actually:

 

Number of errors / discharge = 1 / (Number of pulses to cause an error) 

 

This number is recorded versus the ESD voltage applied by the simulator. Such error/pulse concept allows the replacement of the GO/NO-GO criteria by a better approach, assuming that:

  • The result of each trial is independent from the previous one: chances of hit-or-miss are the same for each trial ; the EUT has no “memory” of the former events.
  • The stimulus of each event is received exactly the same way by the EUT: this assumption is not totally true, since an ESD test carries some uncertainties, but we will accept it.
  • The ocurrence of an UR to an ESD stimuli is of random nature for logic errors only. Component damage is not much related to a “High”/“Low” status of a logic input, but to the coupled energy exceeding the safe limits of the component. Therefore, only logic errors are addressed here.
Fig.14. Error per pulse: due to the random occurrence of ESD pulses vs.logic operations (left), the behavior of a machine during an ESD test is not a step function (A), but a steep slope (B). A minimum number of discharges is necessasry to explore the worst case coincidences of the ESD transient with certain patterns of logic transitions.

Given that a 100% confidence that no error will occur for a given ESD level would require an infinite number of trials, probabilities calculations for large sample sizes can help us:

 

– it is generally sufficient, for ESD-related errors, to guarantee that the machine will not suffer more than Nr errors per day (or shift), or per week; This is application-dependent and can be established, as being what the users can tolerate.

– this number Nr will be confronted with the number of ESD events/ shift exceeding a given voltage, such as in field conditions:

 

Nber of errors/Shift = [ P(Error,V) x N( Event ”V”) per shift ] (4) 

 

with:

 

(Error,V) = Probability that the machine will make an error, given a discharge voltage V.

N (Event ”V”) = Number of ESD events/shift which will equal or exceed V.

 

One can derive such criteria that, for an ESD test:

 

Error rate at given level Vesd = (Tolerable Nber of Errors/Shift) / Nber of Events/Shift ≥ V (5) 

 

Example: Assume a product intended for professional applications. A maximum of one non self-corrected error per 2 days is regarded as acceptable, for the worst periods of the year, provided it does not cause hard damage or loss of stored data (”type B” error). Early prototype ESD test ((using IEC simulator) has shown type B errors appearing above 3kV, for an average number of 30 trials, that is a hit / miss rate of 3%. This correspond to a 11Amp peak current.

How often such discharge current occur ?

For a severe, uncontrolled environment, Event Statistics (Fig.3) show a probability of 3 events / shift exceeding 11A. Therefore, the present product vulnerability is unacceptable. Per Fig.15, reducing to 1 error / 2 shifts, assuming 1 day ≈ one 8 hrs-shift requires the product be hardened up to a 30Amp, corresponding to 8kV test voltage. 

 

Then, how much 8kV discharges should be required in the ESD test plan? Crude answer would be: 1/0,03 or 30 discharges. This is ignoring the probability laws (think of throwing dices ..). On Fig 15, a 3% probability of success with a typical 95% confidence, requires at least 100 trials. Considering that a100% confidence is not achievable, the only residual risk is two-fold:

 

a) accepting a machine that should have been rejected ( number of trials was too low), or,

b) rejecting a machine which made one error, but could have been accepted.

 

An ”escalation strategy” (given as informative annex in recent IEC or ANSI standards) can give some more leeway, allowing for one error if an additional number of zero-error trials is performed.

Fig. 15. Required number of discharges to apply with zero failure, for a given % confidence

8. ESD test during design & development

Given that ESD testing is efficient and relatively easy to conduct, it can be applied to the machine as soon as an early prototype exists and, furthermore, as soon as functional sub-assemblies exist. For instance, an early ESD test is easy to perform on a breadboard prototype using an indirect discharge set-up. A most rewarding approach is to start an ESD immunity e PCB level. Later on, when functional hardware has been designed and a prototype is available, the following is suggested:

 

– Identify the principal boards in the machine; i.e., those which perform essential functions and constitute block-diagrams in the machine architecture.

 

– Prepare each of those boards for testing as a stand-alone items. Equip few lines considered as ”witnesses” of the card’s good condition (for ex. Watchdog, Reset with a LED soldered directly on the board, so that when everything is normal, the LED is OFF. Preferably, provide a stand-alone DC power source (a simple battery pack).

 

– Perform an IESD test of the PCB, as shown in Fig.16. The discharge is applied on a metal plane, the card being placed at a distance which is representative of the actual card-to-housing distance of the future machine. The test voltage depends on the criteria for the final product. If the product is planned with a plastic, non-conductive cabinet, the ESD voltage should be set as for the final product. This test is some of the best invested time in the entire ESD strategy, revealing PCB layout weaknesses at a time when they are relatively easy to correct.

 

– Harden the I/O zones; this remains to be done when the board alone has been brought-up to the desired level. An hardened card can still make errors if ESD-induced glitches enter by the connector pins; (the test done so far involved only the direct radiation pick-up by the board). To this end, a typical length of flat cable, multipair cable or any conductor which replicates the reality is plugged on the card connector(s). The far-end must be terminated to passive resistors, or to an exerciser that simulates the normal I/O transactions with the product.

Fig. 16. Work-bench mounting for early ESD testing of a PCB. The height ”h” can be equaled to the average distance of the PCB from the EUT bottom plate or the closest wall of the housing. By default, use 5 cm.

9. ESD for EMC field diagnostics, and forced crash method

Any system can be viewed as a black box with input/output ports. To the degree a system can be viewed as a two-port network, its transfer function can determined by measuring its response to a step impulse. A handy, easy carried ESD generator can be used as a quick first check of the susceptibility of an equipment to almost any kind of EMI. A properly simulated ESD event can tell more of the weaknesses of a product than its mere vulnerability to static discharges. Although it cannot replace traditional, mandatory EMC tests, the wideband field of an ESD flashes the equipment all at once, revealing some weak spots that a true EMI test will explore. Furthermore, an ESD test is simple to run, hence ideally suited to on-site testing.

 

Forced crash is a technique by which one decides that instead of waiting for a random, hard-to-catch problem to show-up, he intentionally injects into the equipment a fast transient pulse that broadly covers the frequency spectrum of any possible intermittent event, ESD or else. Forcing an EMI failure with an ESD test applied on site is a powerful diagnostic tool, and a very localized stimulus. It will be merciless in pinpointing hardware EMC deficiencies. The pulse is calibrated, progress can be quantified, and a susceptibility map be drawn. Such on-site procedure is rather similar to the ESD test in the lab, but there are differences: you are not testing a development or pre-manufacturing unit with diagnostic tools, but a machine actually in service. Make sure that the test does not lead to a risk of material damage, or even safety hazard. Try to inhibit temporarily any peripheral that could create such risk.

 

Once quick field-fixes have been applied (Ref.9), re-run a test to see if the ESD critera are now met, including on all zones that were previously okay: a local improvement may have caused a degradation in another place. Never remove a fix that seems to bring no improvement: add them up to the final success. The philosophy behind this is that if a unit at its site, with all external cables and peripherals in place, is fixed to 8kV ESD, it will probably be” vaccinated” against any type of short, fast-rising transients, even if the actual reason for the field problem is never to be found.

Home-made Investigation Tools, and Diagnostic Hints

Investigating ESD suceptibility after a failed test, or an actual field problem, can be very frustrating for someone with no experience or knowledge of the ESD coupling mechanisms. On the contrary, with some background and a minimum set of appropriate diagnostic hardware, it will turn into a rewarding experience. Besides the ESD simulator, a few basic tools are needed (more on this subject can be found in Ref 9):

 

– a fast digital memory oscilloscope, with an equivalent analog bandwidth of at least 500MHz, corresponding to the 3dB bandwidth for a 0.7 ns rise time.

– an E-field injection adapter (discoidal electrode fitted to the gun tip for E-field enhancement).

– an H-field injection adapter ( Moebius loop), to mount on the gun tip.

– a shielded, EMI passive current probe, with useable 500MHz bandwidth and preferrably a flat response (transfer impedance) for the 3 – 300MHz range.

 

Because of the localized area that they cover, the two field-enhancement adapters can help finger-pointing equipment weaknesses like shielding deficiencies, breeches in a PCB ground plane, unfiltered (or poorly filtered) input ports.

 

 

Michel Mardiguian
EMC Consultant, France
m.mardiguian@orange.fr

 

REFERENCES

  1. Simonic,R. Personnel ESD Statistics . IEEE-EMC Symposium, 1981
  2. Mardiguian,M. ESD, Wiley, 3rd edition 2009
  3. IEC 61000-4-2 ElectroStatic Discharge Immunity Test (2008 )
  4. ANSI C63-16 Standard for ESD Test Methodology and criteria (2005)
  5. Pommerenke,D., Frei,S. Analysis of fields on H.C. Plane in ESD test. Journal of ElectroStatics, N°44 (1998)
  6. Calcavecchio,R. A standard test to determine ESD susceptibility. IEEE/ EMC sympos. 1986 
  7. Pratt,D., Davis,J. ESD failure rate prediction IEEE/EMC sympos. 1984
  8. Boxleitner,W. ESD and Electronic equipment, IEEE Press, 1989
  9. King, M. “Mastering ESD System response”. EMC Technology Magazine, March & May 1988
  10. Mardiguian,M. EMI Troubleshooting techniques. Mc Graw Hill, 2000 
  11. IEC 61340-5.1 and 5.2 Anti-Static Control Procedures